Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a Lead RTL Design Engineer, you will be responsible for architecting and implementing RTL for next-generation high-speed Ethernet IP cores, 100G and beyond, targeting Enterprise, Commercial, and Automotive applications.
Key responsibilities include:
- Translating protocol specifications into detailed micro-architecture and design documentation
- Owning the full design flow from RTL coding through synthesis, CDC analysis, formal verification, and debug
- Leading design tasks as an individual contributor and technical guide, mentoring designers on architecture decisions and design quality
- Collaborating with global verification teams on test planning, coverage strategies, and verification closure
The ideal candidate will have a deep understanding of industry protocols, such as Ultra Accelerator Link, Ethernet, DDR, PCIe, or USB, and experience in architecting control path logic, including asynchronous FIFOs, DMA architectures, and SPRAM/DPRAM interfaces.
This is a global team of expert engineers spread across multiple sites, and you will collaborate closely with RTL designers, verification engineers, and customers on technically challenging IP development.
At Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.