Description
You are a recognised technical leader in high-speed memory interface design, with deep expertise spanning architecture, circuits, and system-level integration. You operate at a mastery level and are known for your ability to guide teams through complex technical challenges while influencing direction through credibility and trust rather than authority alone.
You bring extensive experience in many of DDR, LPDDR, HBM, die-to-die and SerDes interfaces, with a strong foundation in signal integrity, power integrity, and high-speed I/O design. You are comfortable working from early pathfinding and architecture definition through to productization, and you understand how to translate market needs and customer requirements into scalable, high-performance PHY solutions.
You are naturally seen as a leader,someone others turn to for direction, clarity, and confidence. You build trust quickly, elevate those around you, and create an environment where teams can execute with autonomy and accountability. Whether or not you have formal direct reports, your impact is measured by how teams align behind you and deliver.
You thrive in a fast-paced, innovation-driven environment and are motivated by solving hard problems that push the boundaries of performance, speed, and efficiency.
Key Responsibilities:
- Leading architecture and pathfinding activities for next-generation Memory PHY solutions (DDR, HBM, LPDDR, D2D, SerDes)
- Driving development of advanced circuit solutions for high-speed interfaces, including I/O design, link design, and signal/power integrity optimisation
- Translating customer requirements and industry trends into scalable PHY architectures and product definitions
- Guiding and influencing global engineering teams (architecture, design, verification) to deliver best-in-class IP solutions
- Providing technical leadership across the organisation, mentoring engineers and strengthening overall capability in advanced circuits and PHY design
- Partnering with senior leadership to implement strategic goals with significant impact on business and product direction
- Engaging with key customers and industry stakeholders to shape roadmap and maintain Synopsys' leadership in Memory IP
- Driving innovation in performance, speed scaling, and design methodologies for next-generation interfaces
Impact:
- Define and influence the future of Synopsys Memory PHY architecture across DDR and HBM portfolios
- Enable next-generation AI, HPC, and data centre systems through leading-edge interface technologies
- Elevate the technical capability of the organisation through mentorship, coaching, and leadership by example
- Drive alignment across teams and functions, ensuring successful execution of complex, high-impact programmes
- Position Synopsys as a continued leader in high-speed interface IP through innovation and customer engagement
- Build trust and confidence across the organisation as a go-to technical authority
Requirements:
- 15–20+ years of experience in high-speed interface or memory PHY design (or equivalent depth of expertise)
- Proven experience with DDR, LPDDR, HBM, and/or die-to-die / SerDes technologies
- Strong background in:
PHYS architecture and pathfinding High-speed I/O design and link design Signal integrity and power integrity Advanced circuit design for high-performance interfaces Track record of delivering complex products from concept through silicon Demonstrated ability to influence large, cross-functional teams without formal authority Experience working with customers and translating system requirements into product solutions PhD or equivalent experience in Electrical Engineering or related field preferred