Description
We are now looking for an ASIC Design Efficiency Engineer to join our dynamic team. As an ASIC Design Efficiency Engineer, you will develop innovative HW, GPU and system designs to extend the state of the art performance and efficiency. You will understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements. You will execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets. You will collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.
The ideal candidate will have a Bachelor's Degree in EE or CE or equivalent experience, 2+ years of experience, proficiency in SystemVerilog or similar HDL, a solid understanding of logic design and computer architecture, and strong interpersonal skills. A background in pipeline processor or deep learning accelerator design/architecture, performance verification, low power or physical (synthesis/VLSI) design, and scripting knowledge in Python/Perl is highly desirable.
You will be eligible for equity and benefits, and will work in a diverse product-oriented team. Applications for this job will be accepted at least until May 25, 2026.