Description
At Synopsys, we power the innovations that define the Era of Pervasive Intelligence , from autonomous systems and AI accelerators to the most advanced silicon on the planet. As the leader in EDA, semiconductor IP, and hardware-assisted verification, we partner with the world's most ambitious chip designers to deliver the technology that turns ideas into silicon.
You are a highly skilled R&D engineer who is energized by working deep in the core internals of a large, mission-critical EDA product. You take pride in writing robust, performant, and maintainable C++ on UNIX/Linux, leveraging modern IDEs and AI-assisted developer environments to accelerate development. You have a deep appreciation for the data structures, memory layouts, and algorithmic choices that determine whether a tool scales gracefully to billion-gate designs and enjoy reasoning about netlist representations, graph traversals, hashing strategies, and the subtle trade-offs between runtime, memory footprint, and capacity.
You communicate clearly and employ a methodical approach to solving complex problems. You see software craftsmanship , clean interfaces, disciplined testing, and measurable improvements , as the foundation of long-term product health.
As a Staff Engineer on the Formality R&D team, you will drive runtime, memory, and capacity improvements profiling production designs and re-engineering hotspots to deliver step-function gains. You will design and harden parallel architectures to scale equivalence checking to modern multi-core machines. You will take end-to-end technical ownership of complex customer escalations rooted in layers , reproducing, root-causing, fixing, and adding the safeguards that prevent regression.
The impact you will have is defining the structural and performance ceiling of Formality, directly enabling our customers to sign off larger and more complex designs with confidence. You will strengthen the long-term architectural foundation of a flagship Synopsys product trusted across every major semiconductor company. You will influence the technical direction of the team through design leadership, mentorship, and a strong example of engineering rigor.
Key responsibilities include:
- Architect, develop, and own core infrastructure of the Formality verification engine.
- Drive runtime, memory, and capacity improvements profiling production designs and re-engineering hotspots to deliver step-function gains.
- Design and harden parallel architectures to scale equivalence checking to modern multi-core machines.
- Take end-to-end technical ownership of complex customer escalations rooted in layers , reproducing, root-causing, fixing, and adding the safeguards that prevent regression.
- Initiate design reviews, raise the bar on code quality and unit-test coverage.
- Collaborate across teams to enable the abstractions needed for future capabilities.
What you'll need:
- BE/B.Tech in Computer Science, Electrical, or Electronics Engineering with strong relevant experience, or an MS / PhD in a related discipline.
- 5+ years (BE/B.Tech), 3+ years (MS), or 2+ years (PhD) of professional software development experience in large, production C++ codebases, with demonstrated module ownership and technical leadership on non-trivial features.
- Expert command of modern C++, the STL, templates, and idiomatic memory and lifetime management for performance-sensitive systems.
- Strong fundamentals in data structures and algorithms , graphs, hash tables, trees, traversal and BDD , with a track record of applying them to real engineering problems.
- Demonstrated ability to profile, diagnose, and optimize for runtime, memory, and scalability on multi-million-instance workloads.
- Working knowledge of HDLs (Verilog / SystemVerilog / VHDL) and digital design fundamentals; familiarity with synthesis, equivalence checking, or related EDA flows is strongly preferred.
- Comfort with TCL, Python, and shell scripting for tool infrastructure, regressions, and developer tooling.
- Exposure to AI-assisted developer tools such as Cursor or GitHub Copilot, and a curiosity for adopting modern productivity practices.
- Excellent written and verbal communication, with the ability to lead technical discussions across teams.
What you are:
- A systems thinker who understands how a small change deep in the system ripples through the entire product.
- A disciplined engineer who values measurement over intuition and tests over hope.
- A mentor and collaborator who lifts the technical quality of everyone around you.
- A pragmatic problem-solver who balances long-term architecture with short-term delivery.
- A continuous learner who keeps pace with advances in C++ and EDA methodology.
The team you'll be a part of: You will join the Formality R&D team , the group responsible for the structural backbone of one of the industry's most established formal equivalence checking tools. We own the data, the infrastructure, and the performance characteristics that every other Formality capability is built upon. The team values deep technical ownership, careful engineering, and a culture where strong opinions are tested against data. You will work alongside experienced engineers solving problems at the limits of design size, with broad exposure to formal verification, synthesis, and large-scale software systems.