ASIC Design Engineer, BOOT and Power Management

NVIDIA is seeking an RTL Design engineer for its BOOT and Power management Subsystem Design deployed in Automotive and Client chips. As one of the primary designers, you will be responsible for implementing system BOOT and overall power management architecture of next-generation chips.

The ideal candidate will have strong digital design and verification fundamentals. Key responsibilities include:

• Making architectural trade-offs based on feature/performance/power requirements
• Analyzing system implications and coming up with the micro-architecture
• Implementing RTL and driving verification
• Closing timing and supporting silicon validation
• Owning micro-architecture and RTL development of design modules
• Micro-architecting features to meet performance, power, and area requirements
• Collaborating with HW architects to define critical features
• Working with verification teams to verify the correctness of implemented features
• Partnering with timing, VLSI, and Physical design teams to ensure design meets timing, interface requirements, and is routable

Requirements:

• BTech/MTech with 2+ years of experience in crafting complex Units and CPU/micro-controller-based Sub-systems
• Knowledge of security standards, protocols, and system security architectures of modern SOCs (significant plus)
• Excellent influencing skills for collaboration with cross-cultural, multi-geography, and matrixed teams
• Good debugging, analytical, and problem-solving skills
• Great interpersonal skills and ability to work as an excellent teammate

NVIDIA offers highly competitive salaries and a comprehensive benefits package.