Senior ASIC Design Engineer - XBAR IP

We are seeking a Senior ASIC Design Engineer to join our Graphics team. In this position, you will be responsible for designing state-of-the-art memory subsystem components used in our industry-leading Graphics Processors. Your work will have a real impact on product lines ranging from consumer graphics to self-driving cars and artificial intelligence.

Key responsibilities include:

• Making architectural trade-offs based on features, performance requirements, and system limitations
• Developing micro-architecture and implementing in RTL
• Collaborating with architects, designers, verification teams, synthesis, timing, and backend teams
• Ensuring design meets timing, interface requirements, and is routable

Requirements include:

• Bachelor's or Master's degree in Electrical Engineering or Computer Science
• 5+ years of design experience
• Experience in RTL design of complex design units for at least two or three projects
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug

Preferred qualifications include:

• Design experience in memory subsystem or network interconnect IP
• Good debugging and problem-solving skills
• Scripting knowledge (Python/Perl/shell)
• Leadership experience in leading small 2-3 member teams
• Good interpersonal skills and ability & desire to work as a part of a team