Senior ASIC Verification engineer

We're seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of IST IPs for the world's leading GPUs and SOCs.

As a Senior Verification Engineer, you will be integral part of team in Bangalore and will be responsible for chip level verification of High-Speed Test Access Mechanism (TAM) that can be used for Automatic Test Equipment (ATE) based testing, System Level Testing, In Field Testing, Predictive In Field Testing extending into Silicon life cycle management (SLM).

Responsibilities:

• Understand architecture/design and write test plans that are efficient yet exhaustive in coverage.
• Development of test environment such as creation/modification of testbench, updates to software sequences, creation/integration of checkers from UV.
• Execute the test plan, review results with arch/design teams for final signoff.
• Close collaboration with Emulation/FPGA teams to enable our tests and verify the tests on post silicon.
• Innovative optimizations to reduce simulation time and improve verification work flows.
• Work with HW architects and designers to make the right implementation choices to optimize the whole pipeline.

Requirements:

• B.Tech/M.Tech or equivalent experience.
• 4+ years of relevant experience.
• Expertise in verification at sub-system/SOC level and expertise in Verilog and SystemVerilog.
• Expertise in debugging functional and toggle coverage.
• Some experience in UVM is good to have.
• Proficiency in grasping feature requirements for intricate features at the system level and devising test plans to validate them.
• Strong problem-solving skills.
• Strong interpersonal and team building skills with proficiency in written and verbal communications.

Nice to Have:

• Grasp of system architecture concepts in the context of fullchip verification, like interrupts, error collators, handshakes, IO handling etc.
• Expertise in protocols like APB/AXI/CHI.
• Experience with JTAG and DFT concepts like mbist/lbist.