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NVIDIA

Senior Silicon Product Development Engineer

NVIDIA
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onsite senior full-time Santa Clara

First indexed 18 May 2026

Description

Are you prepared to step into a vital position within a top-tier organisation? In the role of Senior Silicon Product Development Engineer at NVIDIA, you will be instrumental in launching our brand-new Data Center products. This role offers an outstanding opportunity to work alongside a world-class team and use your expertise to impact GPU production yields and optimize test time forecasts.

Your contributions will directly improve the quality and performance of our ground-breaking silicon products.

Responsibilities:

  • Own the development and implementation of ATE test content for our product line.
  • Impact GPU manufacturing yields, minimise excess, and contribute to business administration efforts by accurately predicting test durations and analysing characterisation outcomes.
  • Develop and maintain failure analysis plans to strictly adhere to yield improvement.
  • Manage key vendor relationships, particularly with Foundry, Assembly, and Memory vendors, ensuring flawless collaboration and delivery.
  • Collaborate closely with Supply and Demand program management to meet and exceed chip quality levels.

Requirements:

  • Bachelor or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
  • 7+ years of direct PDE experience.
  • Strong problem-solving skills and a proven track record in ASIC Mixed Signal build, characterisation, and qualification of BIST and SCAN DFT methodologies.
  • Knowledgeable in advanced Silicon Process technology such as FinFET.
  • Hands-on experience in Chip-On-Wafer-On-Substrate Assembly, Silicon GPU Product Engineering, and HBM Memory vendor management.
  • Excellent interpersonal skills for effective multi-functional and cross-company collaboration.

Ways to stand out from the crowd:

  • Possesses in-depth knowledge of advanced technology node, assembly stacking processes, and vendor management.
  • Has a strong grasp of all aspects of Silicon characterisation, wafer sort, and final test DFT coverage.
  • Demonstrates comprehensive understanding of Silicon failure analysis technique.