Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification.
You will develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.
You will apply layout matching techniques and address ESD, latch-up, EMIR, DFM, and LEF generation issues. You will collaborate closely with cross-disciplinary teams to optimize layout for performance, power, and area.
You will troubleshoot and debug layout challenges, continually improving methodologies and design outcomes. You will document design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.
Accelerating the integration of advanced silicon IP into customer SoCs, ensuring robust and reliable IP performance through meticulous layout design and physical verification, driving innovation in memory interface IPs, and reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.