Description
We are seeking a Senior ASIC Design Engineer to join our High Speed IO IP team. As a senior designer, you will be responsible for understanding specific protocol concepts and features, making architectural trade-offs based on feature/performance/power requirements, analysing system implications, coming up with the micro-architecture, implementing RTL, driving the verification, closing timing, and supporting silicon validation.
Your responsibilities will include owning micro-architecture and RTL development of design modules, micro-architecting features to meet performance, power, and area requirements, working with HW architects to define critical features, working with verification teams to verify the correctness of implemented features, and working with timing, VLSI, and physical design teams to ensure design meets timing, interface requirements, and is routable.
To be successful in this role, you should have a BTech/MTech in EE, ECE, or a similar stream, with a proven track record of 3+ years of experience in crafting complex units and CPU/micro-controller-based subsystems. Knowledge of HSIO standards, protocols, and architectures of modern SOCs would be a significant plus. Excellent influencing skills resulting in collaboration with cross-cultural, multi-geography, and matrixed teams are also essential.
If you're creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you!