Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a DFT Senior/Staff Engineer, you will own DFT tasks at IP level, including scan chain stitching, ATPG, and simulation. You will create timing constraints for mission and DFT modes, work with design and physical implementation teams on synthesis and constraint validation, support customer IP integration and silicon bring-up, and lead and coach DFT team members.
The impact you will have includes improving testability and quality of IP cores, speeding up time-to-market for new chips, supporting seamless SoC integrations for customers, and mentoring team members and sharing best practices.
To be successful in this role, you will need a BS/MS/PhD in Electronics or a related field, 2+ years DFT design experience, expertise in scan insertion, ATPG, JTAG, and experience with Synopsys tools (Design Compiler, VCS, TetraMAX) is a plus. You will also need scripting skills (Perl, TCL, Python) and be detail-oriented, analytical, and a strong communicator.
Join our expert DFT Engineering team in Ho Chi Minh City, dedicated to advancing testability and reliability in semiconductor IP.