Senior Power Integrity Methodology CAD Engineer

We are now looking for a Senior Power Integrity Methodology CAD Engineer.

As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. You will develop physical design methodologies for rail analysis and signoff, come up with unique and creative solutions for pioneering IR analysis and signoff, and craft workflows and tool methodologies for power and noise analysis across multiple projects.

Responsibilities:

• Develop physical design methodologies for rail analysis and signoff.
• Responsible for coming up with unique and creative solutions for pioneering IR analysis and signoff that are needed for NVIDIA chips.
• Crafting workflows and tool methodologies for power and noise analysis across multiple projects.

Requirements:

• Master's degree or equivalent experience in Electrical Engineering or related field.
• Minimum 5+ years of experience in EMIR flow methodology development and support.
• Strong understanding of all aspects of EMIR analysis and signoff.
• Familiar with hierarchical design approach and hierarchical signoff.
• Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
• Ability to collaborate across teams: Strong interpersonal, communication and teamwork skills, with a track record of working closely with hardware and design teams to facilitate EMIR signoff.
• Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.

Benefits:

• Eligible for equity and benefits.