Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent a decade deep in PCI Express, and you know the specification the way most people know their commute. You have read the errata, tracked the ECNs, and debugged corner cases that only show up when three features collide in a way the spec never quite spelled out. You are the person teams pull into a room when something does not make sense. You have lived on both sides of the verification equation. Maybe you built Verification IP, maybe you used it to validate complex controller and PHY designs, but either way, you understand the gap between what a VIP can do and what a design team actually needs. That gap frustrates you, and you have strong opinions about how to close it. You think in requirements and traceability. Working across geographies and functions does not slow you down. You communicate clearly, align stakeholders without drama, and get results.
Own the alignment between Verification IP capabilities and Design IP verification needs, identifying gaps in feature coverage for both Controller and PHY Drive requirements definition for Verification IP based on real Design IP verification use cases Track PCI Express specification updates, ECNs, and errata, translating changes into actionable requirements for both VIP and Design IP teams Review and critique testplans across projects, pushing teams toward best-in-class coverage and traceability Report VIP deployment metrics and drive continuous improvement in how VIP is integrated into verification flows Work hands-on with UVM-based verification environments to validate VIP usage and model best practices
You will close the gap between what Verification IP delivers and what Design IP teams actually need Your work will shift verification left, catching issues earlier and reducing costly respins downstream You will change how teams think about VIP as a strategic asset that evolves with design needs Your protocol expertise will ensure Synopsys PCIe and CXL IP stays ahead of specification changes You will standardize verification workflows, raising the bar for testplan rigor and coverage discipline You will improve cross-functional collaboration between VIP and Design IP teams, reducing friction and improving product quality
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.