Description
We are looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms.
As an ASIC STA Engineer, you will be responsible for full chip and/or chiplet level STA convergence from early stages to signoff. You will also take part in top-level floor plan and clock planning, optimize CAD signoff flows and methodologies, and integrate digital partitions' and analog IPs' timing. Additionally, you will work closely with logic design and DFT engineers to define and implement constraints for various work modes, including their optimization for runtime and efficiency.
To be successful in this role, you will need a B.Sc./M.Sc. in Electrical Engineering/Computer Engineering, 3+ years of experience in physical design and STA, proven experience in RTL2GDS and STA design and convergence, familiarity with physical design EDA tools, and hands-on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts is required.
As a member of our team, you will have the opportunity to work on cutting-edge projects, collaborate with talented engineers, and contribute to the development of innovative products.