Layout Design, Sr Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We are seeking a highly skilled Layout Design, Sr Engineer to join our team in Ho Chi Minh City. As a key member of our engineering team, you will be responsible for designing and integrating memory leafcell layouts and standard cell layouts using Custom Compiler, optimizing for area, speed, and power across advanced FinFET technology nodes.

Responsibilities

• Design and integrate memory leafcell layouts and standard cell layouts using Custom Compiler, optimizing for area, speed, and power across advanced FinFET technology nodes
• Run and debug physical verification flows including DRC, LVS, ERC, and antenna checks using ICV, resolving violations down to clean tapeout-ready results
• Collaborate with circuit designers and verification engineers to ensure layout matches design intent and meets performance targets
• Build layout automation scripts in Perl, Shell, or TCL to accelerate repetitive tasks and improve consistency across design variants
• Optimize existing layouts for density and performance, identifying opportunities to shrink area or reduce parasitics without compromising reliability

The Impact You Will Have

• Deliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor markets
• Improve silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respins
• Accelerate project schedules by automating layout tasks and verification flows
• Raise the bar for layout quality across the team by sharing best practices and debugging techniques
• Enable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teams
• Help define layout methodologies that scale across multiple process nodes and design families

What You'll Need

• 2+ years of hands-on experience in custom layout, standard cell layout, or memory layout design
• Deep familiarity with FinFET technology nodes and associated design rules, including complex spacing and enclosure requirements
• Proficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platforms
• Strong skills in DRC, LVS, ERC debugging, including resolving complex violations in hierarchical designs
• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
• Experience writing layout automation scripts in Perl, Shell, or TCL

Who You Are

• You approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisions
• You are detail-oriented without being slow, catching subtle issues while knowing when to move forward
• You communicate clearly with circuit designers and verification engineers, translating technical issues into actionable next steps
• You take ownership of your work, and if something breaks downstream, you want to understand why and prevent it from happening again
• You are curious and always learning, whether it is a new tool feature or a layout technique from a colleague

The Team You'll Be Part Of

You will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries. \\ Benefits vary by country and region - check with your recruiter to confirm

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