Formal Verification Engineer

We are seeking an experienced Formal Verification Engineer with strong CPU/GPU and verification fundamentals to work in our Central Formal team. You will craft and optimize formal verification flows across CPU/GPU projects, resolve tool issues for design teams with tool vendors, and verify micro-architecture using formal verification tools.

Key Responsibilities:

• Develop and maintain an integrated end-to-end formal verification flow for the formal verification team.
• Create scripts to automate the verification process.
• Review formal setups and proofs with design and verification teams.
• Maintain and extend assertion libraries, including support for both simulation and FV.
• Identify key behaviours for verification of DUT and create a verification plan.
• Develop verification environment including environment assumptions, assertions and cover properties in context of the verification plan.
• Apply various FV techniques to prove correctness of digital designs.
• Debug RTL to identify causes of failure scenarios.

Requirements:

• Bachelor's/Master's in Electronics & Communications or Computer Science or Electrical Engineering from a reputed engineering college.
• Minimum 2+ years of industry experience on formal techniques for verification.
• Strong analytical skills to tackle hard problems.
• Excellent command of scripting.
• Strong knowledge of architectures of CPU designs and digital logic.
• Good understanding of abstraction techniques for effective verification.
• Hands-on experience with HDLs such as Verilog / System Verilog.
• Understanding of temporal logic assertions.
• Preferable experience with a variety of Formal Verification Tools.
• Strong communication skills are required along with the ability to work in a dynamic product-oriented team and collaborate effectively across sites.