Description
We are seeking a hardworking and motivated Senior Verification Engineer to join our Tegra SoC Memory Subsystem IP verification team. As a Senior Verification Engineer, you will partner with the design and architecture teams to help make the right implementation choices, craft and implement verification test plans, maintain regressions, close coverage and sign off design or both functional correctness and for meeting performance expectations.
Your responsibilities will include developing verification infrastructure (testbenches, BFMs, checkers, monitors, randoms), coming up with, reviewing and driving test plan execution for planned features, understanding the performance requirements of your IP, coming up with, reviewing and driving performance test plan for your IP, ensuring code and functional coverage of all the RTL which you will verify, working with and enabling FPGA and software teams to ensure that software is tested, and planning for and being involved with post-silicon verification and debug.
To be successful in this role, you will need to have a BS/MS or equivalent experience, 3+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown success, exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), background with System Verilog and UVM based methodology for ASIC verification, strong C/C++ programming experience, prior design or verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5, 6}), strong debugging and problem solving skills, and scripting knowledge (Python/Perl/shell).
In addition to a competitive salary and a generous benefits package, you will also be eligible for equity and benefits.