Description
Join the ASIC-PD team at NVIDIA, where you will work on physical design from RTL to GSDII. Your responsibilities will include design quality check, synthesis, formal check, partitioning, constraint creation and validation, timing closure for both partition and full chip level, special timing closure, synthesis, netlist quality check, formal verification, implementing chip partition and floorplan, function eco creation, and developing and enhancing the entire timing closure flow from frontend to backend.
As a member of the team, you will work together with experts in all these areas, driving physical friendly design with all related teams, including ASIC, P&R, DFT, SI, and ARCH. You will also have the opportunity to work on the most advanced process/technology and the biggest chip in the world.
We are looking for candidates with a Master's degree in Electrical Engineering, Computer Science, or Microelectronics, with 1+ year of experience in IC design implementation. You should have hand-on experience in EDA software from Synopsys and Cadence, and be proficient in Python, Perl, or TCL. Excellent English communication skills are also required.