Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
We are seeking a skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for leading block-level and chip-level physical design activities from netlist through final implementation (RTL to GDSII).
Responsibilities
- Leading block-level and chip-level physical design activities from netlist through final implementation (RTL to GDSII).
- Driving floorplanning, power planning, placement, clock tree synthesis, routing, and physical verification tasks.
- Optimizing designs for timing, power, area, congestion, and signal integrity to meet stringent project requirements.
- Partnering with RTL, STA, DFT, packaging, and signoff teams to achieve implementation and closure goals.
- Developing and improving automation scripts and methodologies to increase physical design efficiency and quality.
- Investigating and resolving design, tool, and flow issues throughout the implementation cycle.
- Mentoring junior engineers and providing technical leadership across the team.
Impact
- Delivering high-quality silicon solutions that power advanced technologies and accelerate innovation.
- Ensuring successful implementation and signoff of complex ASIC and SoC programs on schedule.
- Driving improvements in design efficiency, methodology, and automation within the team.
- Enhancing cross-functional collaboration to solve multidisciplinary challenges in chip development.
- Contributing technical leadership and mentoring to foster a culture of growth and excellence.
- Increasing the competitive edge of Synopsys by enabling the creation of high-performance, reliable chips.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Strong experience in ASIC physical design and implementation.
- Hands-on knowledge of full physical design flow, including floorplanning, CTS, routing, timing closure, and signoff support.
- Experience with advanced process nodes and complex SoC integration challenges.
- Strong understanding of STA, IR drop, EM, and physical verification concepts.
- Proficiency with industry-standard implementation and signoff tools such as Synopsys ICC2, Fusion Compiler, PrimeTime, and similar.
- Scripting experience in Tcl, Python, Perl, or similar languages.
- Excellent written and verbal communication skills in English.
- Demonstrated ability to work effectively in cross-functional teams and build strong network relationships.
Team
You'll join a dynamic and highly skilled engineering team focused on delivering world-class ASIC and SoC solutions. The team values collaboration, technical excellence, and continuous learning, working together to solve complex challenges and drive innovation in silicon design.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.