Description
Are you seeking an outstanding opportunity? We are looking for a Senior Photonic Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal & Silicon Photonic Designs.
As a Senior Photonics Layout Engineer, you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness. You will work within a highly collaborative, multidisciplinary team of photonics, CMOS, packaging, and systems engineers to drive next-generation Silicon Photonics (SiPh) and SERDES products.
Layout Execution & Tape-out Ownership: Lead complex, full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions (high-speed/general I/Os, ESD structures). Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation.
Verification & Mitigation: Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions. Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out.
Test Vehicle & Component Development: Own the layout of complex test structures, active/passive full loops, and certification vehicles with large Design of Experiments (DOEs) to optimize for process windows.
Automation & AI-Assisted Workflows: Develop and implement AI-assisted design methods, layout automation scripts, and custom Pcells to improve productivity, reduce development cycle times, and customize DRC/LVS checking flows.
To succeed in this role, candidates must possess a deep technical understanding of advanced node semiconductor fabrication, sophisticated automation capabilities, and a proven track record of first-time success on high-density chip designs.
You will also be eligible for equity and benefits.