Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent years thinking about how chips break and how to catch those failures before they reach a customer. Testability is not an afterthought for you, it is a design decision that happens early, and you see the downstream consequences of every scan chain stitch, every ATPG pattern, every timing constraint you write. When something does not simulate cleanly, you dig in, trace it back, and figure out what actually went wrong.
What You'll Be Doing
- Own end-to-end DFT implementation including scan chain insertion, stitching, ATPG pattern generation, and fault simulation
- Develop and validate timing constraints for mission mode and DFT test modes to ensure coverage without compromising performance
- Collaborate with RTL design and physical implementation teams to integrate DFT structures early and avoid late-stage design churn
- Support customer engagements during IP integration and silicon bring-up, troubleshooting test failures and refining coverage strategies
- Automate repetitive DFT workflows using Perl, TCL, or Python to improve turnaround time and reduce manual error
- Debug complex scan and ATPG issues across large multi-million gate designs using simulation and synthesis tools
- Mentor junior engineers on DFT fundamentals, tool usage, and best practices in testability design
The Impact You Will Have
- Improve test coverage and fault detection rates across Synopsys IP portfolios, directly reducing silicon risk for customers
- Accelerate time-to-market by delivering clean, testable IP blocks that integrate smoothly into customer SoCs
- Enable seamless silicon bring-up by providing robust test infrastructure that catches manufacturing defects early
- Establish and refine DFT methodologies that scale across multiple product lines and geographies
- Reduce customer support load by delivering IP with proven test readiness and clear integration documentation
- Build team capability by sharing knowledge, reviewing designs, and helping newer engineers develop strong DFT instincts
What You'll Need
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
- 5+ years of hands-on DFT experience in scan insertion, ATPG, JTAG, MBIST, and fault simulation
- Proficiency with Synopsys DFT tools such as Design Compiler, DFTMAX, TetraMAX, and VCS
- Strong scripting skills in Perl, TCL, or Python for automating DFT flows and post-processing results
- Experience debugging timing violations, coverage gaps, and simulation mismatches in complex multi-clock domain designs
- Exposure to customer-facing roles or IP integration projects is a plus