SoC Power Architect

We're seeking a highly-skilled SoC Power Architect to join our networking architecture team. As a key member of the team, you will develop architectures, algorithms, models, and methodologies to improve power consumption of our DPU and NIC products across all design life cycles.

Key responsibilities include:

• Developing power-aware architecture requirements and implementation strategies for next-generation products, balancing power, performance, area, and design execution considerations.
• Working closely with board, package, and physical design teams to understand and mitigate design limitations: power delivery, di/dt, thermal, and signal integrity.
• Collaborating across software, ASIC design, verification, and platform teams to drive power improvements end-to-end.

Requirements include:

• Bachelor's or Master's degree in Electrical Engineering or a related field from a known university.
• At least 5 years of experience in ASIC design/uarch/arch/performance.
• Strong EE fundamentals including knowledge of digital design, front-end and back-end practices, power analysis, and characterization.
• Exceptional analytical skills with a passion for solving complex logical and system-level problems.
• Excellent problem-solving, teamwork, and interpersonal communication skills.

Preferred qualifications include:

• Experience as a hardware architect on high-end ASICs.
• Background in computer architecture with a focus on power management, power optimization and characterization, or power modeling.
• Demonstrated track record of power or performance improvements on silicon products.
• Knowledge of physical design back-end practices and their interaction with power architecture decisions.