R&D Engineering, Staff Engineer (Design Verification/ VIP Verification Engineers)

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.

You have spent years building Verification IP that engineers actually trust, not just IP that passes a checklist.

What You'll Be Doing

• Design, develop, and maintain Verification IP using SystemVerilog and UVM for industry-standard protocols including AMBA, PCIe, USB, Ethernet, UEC, UAL, and MIPI
• Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies
• Code sequences, test scenarios, and checkers that drive coverage-based verification across functional and code coverage dimensions
• Debug complex simulation failures across multi-layer protocol stacks, identifying root causes in both VIP logic and customer integration environments
• Enhance existing VIP products for performance, reusability, and scalability as protocols evolve and customer use cases expand
• Support customers during VIP integration and deployment, troubleshooting issues, answering technical questions, and ensuring successful bring-up
• Collaborate with Design IP teams, R&D engineers, and field application teams to align VIP capabilities with product roadmaps and customer needs

The Impact You Will Have

• Your VIP will enable faster, more reliable verification for semiconductor companies building next-generation SoCs and AI-powered products
• Coverage-driven verification strategies you implement will catch critical protocol violations before they reach silicon, saving months of debug time downstream
• Enhancements you make to existing VIP products will improve performance and expand protocol support across the Synopsys IP portfolio
• Customer deployments you support will directly influence how engineers at leading semiconductor companies adopt and trust Synopsys VIP
• Verification plans you create will set the standard for how protocol compliance is validated across complex, multi-protocol designs
• Collaboration with Design IP teams will tighten the feedback loop between design and verification, improving quality across both disciplines
• Your work will contribute to a VIP product line used globally in semiconductor development, affecting how chips are verified at scale

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience
• 5+ years of hands-on experience developing Verification IP
• Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments
• Specializing in NVMe protocols (mandatory) and PCIe (desirable) or Deep working knowledge of at least two industry-standard protocols USB, Ethernet or MIPI
• The ideal candidate should have hands-on experience with BFM, IP, or VIP development and integration.
• The role requires a solid understanding of verification methodologies and protocol compliance. Strong problem-solving skills and the ability to work independently or as part of a team are important.
• Demonstrated ability to create and execute coverage-driven verification plans, including functional and code coverage analysis
• Experience debugging complex simulation failures and resolving issues across protocol layers and integration boundaries
• Experience working directly with customers or field teams during product deployment is a strong plus
• Excellent communication skills and a proactive approach to technical challenges are highly valued.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.