Senior Power Integrity Engineer - LPU Packaging

We are now looking for a Senior Power Integrity Engineer to join our LPU Packaging team. As a Senior Power Integrity Engineer, you will be responsible for defining best-in-class power delivery design and optimization practices from die/package through board, tray, and rack levels for the full product development cycle.

Your key responsibilities will include:

• Defining PDN targets including impedance, droop, noise, and transient response for GPU, HBM, and high-speed SerDes
• Architecting package-level PDNs by collaborating with design teams on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations
• Driving system-level PI design, including board-level PDN planning, decap placement, and VRM interfaces while co-optimizing with SI, thermal, and mechanical teams
• Performing PI extraction and simulation for advanced packages and developing integrated chip–package–board co-simulation flows using industry-standard tools
• Generating and deploying reusable PI models, such as SPICE, S-parameter, and IBIS-AMI, for use by internal and external partners
• Defining and executing comprehensive lab validation plans to correlate measured impedance, noise, and droop against simulation data and specifications
• Debugging complex system-level issues including rail noise, jitter-induced errors, resets, and margin loss during hardware testing and validation

To be successful in this role, you will need:

• MS or PhD in Electrical Engineering or a related field, or equivalent experience
• 12+ years of relevant work experience in Power Integrity
• A strong background in power integrity for high-current, low-voltage rails within large GPUs, ASICs, or CPUs
• Proven ownership of the chip-package-board PDN design and sign-off process
• Hands-on experience with FCBGA, 25D/3D integration, HBM, or similar high-power, high-pin-count packages
• Direct experience in the co-design of bump/ball maps, power/ground planes, and decoupling capacitor networks
• Proficiency with frequency-domain PDN impedance analysis and time-domain transient/droop simulation tools (e.g., PowerSI, PowerDC, Sigrity, RedHawk, Totem, HFSS, SIwave, ADS, or SPICE)
• A deep understanding of board-level PDN design, including stack-up definition, plane partitioning, and VRM placement on high-layer-count accelerator boards
• Experience in executing lab measurements using VNAs, oscilloscopes, and PDN analyzers to correlate measured noise and droop to original specifications

If you have a passion for power integrity and a strong background in electrical engineering, we encourage you to apply for this exciting opportunity.