Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a Staff RTL Design Engineer, you will implement RTL designs in Verilog for SERDES interfaces and IP cores, shaping the foundation of high-speed connectivity products. You will run Spyglass CDC/RDC/Lint and Tmax to catch clock/reset domain issues and ensure code quality from day one. You will create and refine synthesis constraints, dialing in for robust, high-performance ASIC implementations.
You will work side by side with other design engineers to improve digital design flows and develop better methodologies. You will support integration and verification of complex digital blocks within next-generation SERDES architectures. You will write and maintain scripts in Perl, Shell, Python, or Tcl to automate design and verification, freeing up more time for real engineering.
You will keep up with new protocols and standards in high-speed digital design, making sure your skills and our products stay ahead of the curve.
The impact you will have includes pushing forward the development of SERDES IP that sets the standard for speed and reliability in the industry, driving up quality and trust in our silicon by applying rigorous checks, catching issues early, and never letting standards slip, and helping Synopsys stay at the top of the semiconductor world by delivering IP that customers depend on in critical applications.