Senior Memory Controller Verification Engineer

NVIDIA is seeking a Senior Memory Controller Verification Engineer to join their GPU Memory Subsystem IP verification Team. The successful candidate will partner with design and architecture teams to make implementation choices, craft and implement verification test plans, maintain regressions, close coverage, and sign off design for functional correctness and performance expectations.

The role involves:

• Developing verification infrastructure (testbenches, BFMs, checkers, monitors, randoms)
• Creating, reviewing, and driving test plan execution for planned features
• Understanding performance requirements and developing performance test plans
• Ensuring code and functional coverage of all verified RTL
• Working with FPGA and software teams to ensure software testing
• Planning and involvement in post-silicon verification and debug

Requirements include:

• BS/MS or equivalent experience
• 6+ years of ASIC verification experience with complex designs
• Exposure to design and verification tools (VCS, Debussy, GDB)
• Background in System Verilog and UVM-based methodology for ASIC verification

Preferred qualifications:

• Strong C/C++ programming experience
• Prior design or verification experience with dynamic memory controllers (DDR, LPDDR, HBM, GDDR)
• Strong debugging and problem-solving skills
• Scripting knowledge (Python/Perl/shell)
• Good interpersonal skills and teamwork ability

NVIDIA offers competitive salaries and a generous benefits package.