Description
We are seeking a Senior DFT Engineer to join our Design-for-Test Engineering team at NVIDIA. As a member of this team, you will work on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry's most complex semiconductor chips.
The successful candidate will own and work with cross-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression. You will also help develop and deploy DFT methodologies for our next-generation products and mentor junior engineers on test designs and trade-offs, including cost and quality.
To be considered, you should have:
- A BSEE (or equivalent experience) with 5+, MSEE with 3+ years of experience, or PhD in DFT or related domains
- Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation
- Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
- Good exposure to cross-functional areas, including RTL & clocks design, STA, place-n-route, and power, to ensure we are making the right trade-offs
- Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
- Strong programming and scripting skills in Perl, Python, or Tcl desired
- Extraordinary written and oral communication skills with the curiosity to work on rare challenges
NVIDIA offers highly competitive salaries and a comprehensive benefits package, including equity.