Description
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
In addition, you will help develop and deploy DFT methodologies for our next generation products.
You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
We are looking for a Senior DFT Engineer to join our team. The ideal candidate will have a strong background in DFT and experience in implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
The successful candidate will have excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
Strong programming and scripting skills in Perl, Python or Tcl desired.
Extraordinary written and oral communication skills with the curiosity to work on rare challenges.
NVIDIA offers highly competitive salaries and a comprehensive benefits package.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 12, 2026.