Senior Logic Design Engineer

We are now looking for a Senior Logic Design Engineer to join our DGX FPGA Logic Team. As a member of this team, you will take charge of a section of FPGA/CPLD development, focusing on micro-architectural definition, RTL coding, logic debug, synthesis, and timing closure. Supporting verification, implementation, system bring-up, and system-level validation/debug are also part of your duties.

The ideal candidate will have a strong background in FPGA/CPLD and/or ASIC semiconductor designs, with a deep understanding of ASIC/FPGA/CPLD development flow including RTL development, verification, logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug. They will also have excellent communication and interpersonal skills, with the ability to work in a dynamic, distributed team.

Responsibilities:

• Collaborate with the system architecture team to develop FPGA/CPLD design requirements and implement design to meet all specifications and targets.
• Write readable high-quality RTL, synthesis, timing closure, design documentation, schematic review, bring-up, and supporting system-level validation/debug in the lab.
• Collaborate with our design verification and formal verification team to confirm the accuracy of your design.
• Work together with the validation team to carry out in-system tests and measurements in the lab.
• Assist with overall FPGA design activities.
• System bring-up locally as well as at other global sites, with up to 20% travel expected.

Requirements:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent experience.
• 5+ years of experience in FPGA/CPLD and/or ASIC semiconductor designs.
• Verilog/System Verilog expertise required, with a deep understanding of ASIC/FPGA/CPLD development flow including RTL development, verification, logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, distributed team.
• A solid foundation in FPGA/CPLD development and familiarity with FPGA EDA tools from Xilinx, Altera, or Lattice like Vivado, Quartus, or Diamond is highly valued.
• Familiarity with industry-standard protocols such as I2C, SPI, JTAG, PCIE, USB, Ethernet, Encryption as well as languages such as embedded C, Python, Perl is a plus.
• Willingness and ability to travel up to 20% of the time.
• A track record of collaborating across Systems, Firmware, Software, AE, and Operations teams.
• Direct involvement in system bring-ups.

Preferred Qualifications:

• Platform and system design: Strong understanding or practical experiences with system design methodologies including board design, SI and familiarity with schematics and layout tools.
• Cross-functional collaboration: Excel in cross-functional collaboration between firmware and hardware teams, which is crucial during design development, bring up and working through customer issues.
• Automation and AI: Ability to adopt AI to automate tasks efficiently, which includes but not limited to RTL generation, FPGA/CPLD build process and system level validation.