Principal R&D Engineer-18061

You will be a Principal R&D Engineer at Synopsys, working on advanced node physical design, where every nanometer matters. Your critical contributions will enable worldwide EDA designers to extend the frontiers of semiconductors and chip development.

You will partner with Advanced Node Methodology and R&D teams to deliver rapid PPA closure on high-performance designs using Fusion Compiler. You will connect design requirements, DTCO optimization, and EDA engine capabilities to drive measurable improvements in Power, Performance, Area, and Runtime.

Key responsibilities include:

• Partnering with Advanced Node Methodology and R&D teams to deliver rapid PPA closure on high-performance designs using Fusion Compiler
• Connecting design requirements, DTCO optimization, and EDA engine capabilities to drive measurable improvements in Power, Performance, Area, and Runtime
• Prototyping quick solutions using TCL and Perl to validate and extend EDA engine functionality in response to customer and internal challenges
• Collaborating directly with foundry partners to influence technical strategy and execution for advanced node enablement (2nm, 1.4nm, and beyond)
• Analyzing and enhancing RTL2GDS flows, identifying critical path issues, and proposing tangible algorithms or methodology changes
• Leading benchmarking and tape out efforts to validate new methodologies on real, high-performance core designs
• Providing deep technical guidance to both internal teams and external customers on advanced node physical design, including Backside Routing and Std Cell Library analysis

The impact you will have:

• Accelerate PPA closure for next-generation designs, making Synopsys tools the clear choice for high-performance customers
• Shape the direction of EDA engine development by surfacing real-world challenges and demonstrating actionable solutions
• Shorten turnaround times from design concept to tape out, directly impacting customer time-to-market
• Influence foundry technical roadmaps by bringing grounded, design-driven insights to process and tool co-optimization
• Raise the bar for quality of results (QoR) in advanced node flows, ensuring that every new release delivers measurable value
• Enable the deployment of new physical design methodologies that scale across multiple customers and used cases
• Mentor and elevate your peers by sharing best practices, code snippets, and lessons learned from the front lines

Requirements:

• BS or MS in Electrical Engineering, Computer Engineering, or a closely related field with 12+ years of hands-on EDA product development, deployment, and full-flow benchmarking experience, including design tape outs at advanced nodes
• Deep expertise in RTL2GDS flows, including Synthesis, Place & Route, and physical verification for high-performance cores
• Strong scripting skills with TCL and Perl, with a track record of building practical prototypes and workflow extensions
• Demonstrated experience with advanced node technologies (2nm, 1.4nm and below), including Backside Routing and Std Cell Library analysis
• Solid understanding of how Synthesis and Place & Route engines interact to deliver and optimize QoR
• Experience with Synthesis/Optimization cell selection is a plus

Rewards and Benefits:

• Comprehensive medical and healthcare plans
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP, allowing purchase of Synopsys common stock at a 15% discount
• Retirement plans that vary by region and country