Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a Layout Design Engineer, you will be designing and developing standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will also be applying comprehensive sign-off checks to optimize manufacturability, performance, and yield across multiple foundries.
Key responsibilities include:
- Designing and developing standard cell layouts
- Applying comprehensive sign-off checks
- Collaborating with global teams to resolve methodology issues and implement optimized layout designs
- Conducting design reviews and offering constructive feedback to enhance quality and performance
You will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.