Senior GPU Floorplan Design Engineer

NVIDIA is seeking a talented GPU Floorplan design Engineer to design and implement the world’s leading GPU's as part of a completely new team being built in Bangalore.

This role sits at the intersection of architecture, RTL, performance analysis, and physical design, with a strong focus on path forward, early planning, feasibility studies, and physical trade-off exploration.

Responsibilities:

• Working with architects, design leads, physical design leads, and package leads, you will develop and craft and optimize floorplans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect, and floorplan improvement opportunities.
• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
• You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Requirements:

• B.Tech./M.Tech. with 5+ years of experience in floorplan, SOC planning, ASIC Physical design, or related roles.
• A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
• Hands-on experience with chip-level or subsystem-level floorplanning and physical planning.
• Solid understanding of timing, congestion, power distribution, and physical constraints.
• Experience in Verilog, System Verilog, or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R, and timing closure.
• Strong communication and interpersonal skills and ability & desire to work as a great teammate.
• Python, Perl, and C/C++ programming language experience.

Preferred Qualifications:

• Experience in driving development of large-scale ASIC floorplan is a huge plus.