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Synopsys

ASIC Digital Design, Sr Staff Engineer

Synopsys
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onsite senior full-time Bengaluru

First indexed 24 Apr 2026

Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We are seeking a Sr Staff Engineer to lead and drive ownership of critical areas of verification alongside a team of talented verification engineers. The successful candidate will define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for Subsystem. They will specify, build, enhance, and maintain state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL, behavioral models. The candidate will also code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.

Responsibilities

  • Technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.
  • Defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for Subsystem.
  • Specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL, behavioral models.
  • Coding and debugging test cases, including the creation of complex checkers and assertions using System Verilog/UVM.
  • Extracting and reviewing functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.
  • Managing regressions and contributing to the continuous improvement of verification strategies and test environments.
  • Debugging and resolving simulation failures, ensuring root-cause analysis and timely solutions.
  • Working closely with RTL designers and architects to ensure functional correctness.

Impact

  • Enable the successful verification and deployment of high-performance Subsystem in leading-edge SoCs worldwide.
  • Drive quality that powers AI, automotive, cloud, and mobile applications at massive scale.
  • Advance the state-of-the-art in AI-assisted verification methodologies, influencing future verification flows and processes.
  • Contribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins.
  • Collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.
  • Enhance Synopsys' reputation as the premier provider of high-speed connectivity IP Subsystem through engineering excellence and innovation.
  • Bolster Synopsys' leadership in chip design by ensuring our IP verification methodologies set industry standards.

Requirements

  • Bachelor's or Master's degree in electronics/electrical engineering or related field, with 8+ years' experience in ASIC/FPGA Verification.
  • Ability to debug and define robust verification strategies; experience mentoring is a plus for senior candidates.
  • Demonstrated experience in technically leading a team, record of successful collaboration and stakeholder management.
  • Proven expertise in developing System Verilog/UVM-based test environments for complex ASIC designs.
  • Advanced skills in developing and implementing rigorous test plans, checkers, assertions, and coding complex tests.
  • Strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.
  • Experience with interface protocols and IP design/verification processes; knowledge of UCIe/Ethernet/UALink is highly desirable.
  • Hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.

Team

You will join the Synopsys Subsystem team, a group of expert engineers at the leading edge of IP integration. The team works in close partnership with all interface IP groups, tools, methodology, and architecture groups across North America, Europe, and Asia. Together, you drive engineering excellence and deliver high-impact Subsystem that powers the world's most advanced silicon solutions.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

This listing is enriched and indexed by YubHub. To apply, use the employer's original posting: https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-engineer/44408/93635748272