Senior Design Engineer - Memory Subsystem

We are seeking a Senior Design Engineer to join our team working on the design of state-of-the-art memory sub-system components used in our industry-leading GPUs and SOCs. As a Senior Design Engineer, you will be responsible for owning micro-architecture and RTL development of design modules, making architectural trade-offs based on features, performance requirements, and system limitations, and collaborating with architects, designers, verification teams, synthesis, timing, and backend teams to accomplish your tasks.

Key responsibilities include:

• Owning micro-architecture and RTL development of design modules
• Making architectural trade-offs based on features, performance requirements, and system limitations
• Collaborating with architects, designers, verification teams, synthesis, timing, and backend teams
• Ensuring design meets timing, interface requirements, and is routable

Requirements include:

• BS/MS or equivalent experience
• 4+ years of design experience
• Experience in micro-architecture and RTL development of complex designs
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, timing analysis, floor-planning, ECO, bring-up & lab debug
• Expertise in Verilog

Preferred qualifications include:

• Design experience in memory subsystem or network interconnect IP
• Good debugging and problem-solving skills
• Scripting knowledge (Python/Perl/shell)
• Good interpersonal skills and ability & desire to work as a part of a team