Senior ASIC Floorplan Design Engineer

NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world's leading SOCs, CPUs, and GPUs. This position offers a unique opportunity to craft and influence the design and development of the next generation GPU and SoC from early architecture development phase through physical design phase.

Responsibilities:

• Partner closely with multi-disciplinary teams to craft the chip floorplan that optimizes cost/area, performance, and power for a target market
• Drive the floorplan development and collaborate with ASIC and Physical design teams to identify and solve area, interconnect, timing, and floorplan improvement opportunities
• Develop AI workflows and productivity tools to continually improve existing infrastructure for optimizing chip area and speed of execution
• Identify key technical and product risks and work with engineering and management teams to close on risk mitigation strategies

Requirements:

• MSEE/MSCE (or equivalent experience) with broad and deep experience in chip development
• 10+ years of experience
• Experience with developing SOC, CPU, graphics, memory, and I/O sub-systems in the chip
• Ability to multi-task effectively across simultaneous projects and drive the resolution of complex technical issues among multi-disciplinary engineering teams
• Experience with physical design methodologies, chip floorplan, power/clock/reset distribution, DFT, place and route, timing closure, and packaging
• Strong written, verbal, and technical communications skills
• Agentic AI workflows, Python, Perl and/or C++ programming language experience

Benefits:

• Equity
• Benefits