Description
The NVIDIA GPU clocks group is seeking an excellent Senior ASIC Design Engineer to join the team. As a Clocks team member, you will collaborate with other architects, ASIC designers, and verification engineers to design high-frequency and low-power clocks. You will need to engage with multiple teams and design the GPU clocks to satisfy all architectural constraints. Your strong coding skills in Perl or Python or other industry-standard scripting languages will be essential in improving the productivity of the above teams. You will also use your analytical and problem-solving skills to drive issues to close and collaborate with software and silicon solution teams to debug GPU clock silicon bugs in our new products.
Responsibilities: Collaborate with other architects, ASIC designers, and verification engineers to design high-frequency and low-power clocks. Engage with multiple teams and design the GPU clocks to satisfy all architectural constraints. Use Perl or Python to improve the productivity of the above teams. Collaborate with software and silicon solution teams to debug GPU clock silicon bugs in our new products.
Requirements: BS or MS in EE or equivalent experience. 2+ years of meaningful work experience. Validated experience in RTL design (Verilog), verification, and logic synthesis. Strong coding skills in Perl or Python or other industry-standard scripting languages. Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects. Good understanding of backend flows and requirements. DFT knowledge is a plus. Experience in implementing on-chip clocking networks is desirable. Excellent analytical and problem-solving skills. Fluent English (both written and spoken) and excellent communication skills. Good team work spirit, easy to cooperate with team members.