Senior Physical Design Engineer

We are looking for a senior engineer to join our mixed-signal design team building next-generation NVLINK. This position offers the opportunity to have real impact in a dynamic technology-focused company. As a senior physical design engineer, you will be responsible for implementing complex high-performance and low-power SOCs. Your expertise will be invaluable in driving the success of our products, which range from consumer graphics to self-driving cars and artificial intelligence.

Responsibilities:

• Responsible for STA/design constraint for advanced technology nodes.
• Debugging timing violations and rolling in functional, timing ECOs and netlist formal verification.
• Responsible for floor planning and place and route (P&R) of high-performance chip partitions.
• Work on power grid planning, clock tree synthesis (CTS) and timing closure.
• Multi-mode and multi-corner timing closure, RC extraction, cross-talk, IR drop and EM analysis.
• Physical verification including ERC, DRC, LVS, etc.

Requirements:

• BSEE/MSEE or equivalent experience.
• Minimum 5+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology.
• Able to assist in design flow development and debugging.
• Strong analytical and debugging skills.
• Proficiency using Python, Perl, Tcl, Make scripting is desired.