Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a Sr Physical Design Engineer, you will own end-to-end physical implementation for high-performance interface IPs and test chips, taking designs from RTL through synthesis, floorplanning, placement, CTS, routing, and signoff to GDS.
Key responsibilities include:
- Developing and refining timing constraints, performing static timing analysis using PrimeTime, and closing timing across multiple corners and modes at advanced nodes
- Executing power planning, running EM/IR analysis using RedHawk, and ensuring power integrity and reliability signoff for complex subsystem designs
- Performing physical verification using ICV, resolving DRC/LVS issues, and coordinating with foundry teams to ensure manufacturability
- Building and improving implementation flows and CAD methodologies using Tcl, Perl, and Python scripting to automate repetitive tasks and increase design productivity
The ideal candidate will have a strong working knowledge of Synopsys tools, including Design Compiler, ICC2 or Fusion Compiler, PrimeTime, Star-RCXT, ICV, and RedHawk. You should also have solid understanding of deep sub-micron design challenges, including timing closure, power integrity, EM/IR analysis, and physical verification at 16nm or below.
If you are a motivated and experienced engineer looking to take on new challenges, please apply now!