Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
This role is part of the Synopsys Subsystem team, which works in close partnership with all interface IP groups, tools, methodology and architecture groups across North America, Europe, and Asia. Together, you drive engineering excellence and deliver high-impact Subsystem that powers the world’s most advanced silicon solutions.
As a Staff Engineer, you will lead and drive ownership of critical areas of verification alongside a team of talented verification engineers. You will define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for Subsystem.
Key responsibilities include:
- Defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for Subsystem.
- Specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL, behavioral models.
- Coding and debugging test cases, including the creation of complex checkers and assertions using System Verilog/UVM.
- Extracting and reviewing functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.
- Managing regressions and contributing to the continuous improvement of verification strategies and test environments.
- Debugging and resolving simulation failures, ensuring root-cause analysis and timely solutions.
In this role, you will have the opportunity to work on advanced UCIe/Ethernet/UALink IP integration deployed in the most innovative SoCs. You will collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.
To succeed in this role, you will need:
- Bachelor's or Master's degree in electronics/electrical engineering or related field, with 8+ years’ experience in ASIC/FPGA Verification.
- Ability to debug and define robust verification strategies; experience mentoring is a plus for senior candidates.
- Demonstrated experience in technically leading a team, record of successful collaboration and stakeholder management.
- Proven expertise in developing System Verilog/UVM based test environments for complex ASIC designs.
- Advanced skills in developing and implementing rigorous test plans, checkers, assertions, and coding complex tests.
- Strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.
- Experience with interface protocols and IP design/verification processes; knowledge of UCIe/Ethernet/UALink is highly desirable.
- Hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.
If you thrive in a fast-paced, high-impact engineering environment and are driven by a sense of ownership and technical rigor, you will find Synopsys Subsystem organization to be the ideal environment to accelerate your career and make a meaningful impact.