Senior ASIC Timing Engineer

We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

The successful candidate will lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level. They will collaborate with cross-functional teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.

Key responsibilities include:

• Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
• Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
• Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology.

Requirements include:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5 years' experience or MS (or equivalent experience) with 3 years' experience in Timing and STA.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
• Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power.
• Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
• Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Preferred qualifications include:

• Background in domain specific STA and timing convergence, such as GPUs, CPUs, LPU or SOCs.
• Background in logic synthesis and equivalence checking/FV.
• Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
• Understanding and timing closure of digital logic/macros in AMS designs/IPs.
• Experience in methodology and/or flow development as well as automation.