Physical Design Engineer

We are now looking for VLSI Physical Design Engineers in Hsinchu office, Taiwan. Our team utilises the latest process technology, advanced EDA tools, and sophisticated design methodology. We work on the most challenging designs, pushing for performance limits.

Key Responsibilities:

• Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimisation, place & route, timing closure, power/signal integrity analysis, and physical verification.
• Troubleshoot a wide variety of design and flow complicated issues, applying proactive intervention.
• Collaborate with RTL, DFT, and Circuit designers to ensure high-quality design implementation.

Requirements:

• Bachelor's degree in Engineering or Science or equivalent experience.
• Power user of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk).
• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes.
• 2+ years of experience in above areas.

Preferred Qualifications:

• Master's degree in Engineering or Science.
• Knowledge in FinFET technology, circuit design, and package design.
• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre).
• Proficiency in Perl, Python, TCL, and Makefile scripts.