Description
We are seeking a System Verification Engineer to join our Emulation division and work onsite from our Santa Clara, CA headquarters.
As a System Verification Engineer, you will support multiple emulation environments using the latest emulation techniques, including C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, and Accelerated UVM Testbenches.
Your responsibilities will include bringing up GPUs, SOCs, Switch, and NIC on emulation, root causing system level test fails and emulator environment issues, and bringing up and verifying High Speed protocols such as PCIe, CXL, NVLINK, IB, and Ethernet.
You will also collaborate with Design, DV, Power, Silicon Validation, Performance, and Software teams, work constructively leading emulation vendors to debug issues using various tools, and write monitors and checkers that aid debug in HW test issues and FW/SW bring-up.
To be successful in this role, you will need a M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field with 4+ years of proven experience.
You should be proficient in Verilog and/or VHDL, C/C++, and SystemVerilog, and have protocol knowledge of at least one of the High-speed interfaces: PCIe, CXL, NVLINK, IB, or Ethernet.
Experience with UVM verification environments and scripting with Perl, Python, and C/C++ is essential, as well as familiarity with hierarchical design approach, top-down design, SoC, and system level verification.
Zebu emulation experience with SOC/CPU is also preferred.