Description
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
As a SerDes Signal Integrity (SI) Lead, you will define and maintain SerDes SI requirements for PCIe/Ethernet products. You will develop SI strategy with the 3DIC team (bump-map, package escape, channel feasibility). You will lead SI investigations and document findings. You will participate in industry SI workgroups and apply evolving standards. You will sign off on testchip SI and RX/TX PFE design reviews. You will support customer deliverables and debug interactions.
This role requires expertise in SerDes SI for PCIe/Ethernet (128Gbps+, 200Gbps+). You will need experience with IBIS-AMI, ADS, Matlab, HFSS, and simulation correlation. You will also need knowledge of industry SI requirements and workgroups. Proven leadership in SI investigations and documentation is essential.
As a member of our elite R&D group, you will collaborate with industry-leading SI, design, and verification experts. You will have the opportunity to advance SI methodology and best practices at Synopsys.