Mixed-Signal AMS Co-Simulation Verification Engineer

We are seeking a Mixed-Signal AMS Co-Simulation Verification Engineer to join our team. As a key member of our IPG division, you will be responsible for defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.

What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Experience with AMS tools such as HSPICE, XA, Custom Sim, VCS, and scripting languages like Python, Perl, and UNIX shell.