Senior Verification Engineer, Memory Subsystem

As a Senior Verification Engineer, Memory Subsystem at NVIDIA, you will be responsible for verifying the ASIC design, architecture, and micro-architecture using advanced verification methodologies. You will work closely with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Your responsibilities will include:

• Verifying the correctness of the design using advanced verification methodologies
• Developing the verification infrastructure and defining the verification scope
• Coming up with test plans, tests, and verification infrastructure for complex IPs/sub-systems
• Performing functional coverage driven verification closure
• Building reusable bus functional models, monitors, checkers, and scoreboards following coverage driven verification methodology

We are looking for a candidate with:

• B.Tech./ M.Tech. with 4+ years of relevant experience
• Experience in verification of complex IPs/units and sub-systems
• Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies
• Expertise in Verilog
• Knowledge in SystemVerilog or similar HVL
• Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Preferred qualifications include:

• Experience in memory subsystem or network interconnect IP verification
• Good debugging and analytical skills
• Scripting knowledge (Python/Perl/shell)
• Good communication skills & dream to work as a great teammate

If you are a motivated and detail-oriented individual with a passion for verification engineering, we encourage you to apply for this exciting opportunity.