ASIC Verification- Staff Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications.

Responsibilities

• Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.
• Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.
• Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.
• Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.
• Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.
• Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.
• Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

Impact

• Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.
• Drive innovation in verification methodologies, setting new standards for efficiency and coverage.
• Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle.
• Strengthen Synopsys' reputation as a leader in silicon IP and verification through technical excellence and customer focus.
• Mentor and support junior engineers, fostering a culture of learning and continuous improvement.
• Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

Requirements

• BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.
• Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
• Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.
• Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.
• Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.
• Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.
• Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Who You Are

• Analytical thinker with strong problem-solving and debugging skills.
• Excellent verbal and written communication abilities.
• Team player who thrives in collaborative, multi-site environments.
• Proactive, self-motivated, and able to take initiative on challenging projects.
• Detail-oriented, quality-focused, and driven by a desire to excel.
• Adaptable and eager to continuously learn and apply new technologies.