Description
As a Verification Engineer, Memory Subsystem at NVIDIA, you will be responsible for verifying the ASIC design, architecture, and micro-architecture using advanced verification methodologies. You will work closely with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
Your responsibilities will include:
- Verifying the correctness of the design using advanced verification methodologies
- Developing test plans, tests, and verification infrastructure for complex IPs/sub-systems
- Building reusable bus functional models, monitors, checkers, and scoreboards following coverage-driven verification methodology
- Performing functional coverage-driven verification closure
To succeed in this role, you will need to have a strong understanding of verification methodologies, including random stimulus, functional coverage, and assertion-based verification. You will also need to have expertise in Verilog and knowledge in SystemVerilog or similar HVL. Familiarity with verification methodologies like UVM/VMM and exposure to industry-standard verification tools for simulation and debug is also required.
In addition to your technical skills, you will need to have good debugging and analytical skills, as well as good communication skills and a desire to work as a great teammate.