Senior Director R&D Engineering (Interface PHY / Ethernet SerDes)

You will lead the team building 112G and 224G Ethernet SerDes IP that powers AI infrastructure and hyperscale data centers.

Job Description

As a Senior Director R&D Engineering (Interface PHY / Ethernet SerDes) at Synopsys, you will lead an R&D organization developing 112G/224G Ethernet SerDes and Interface PHY IP for AI/HPC, networking, and data center markets.

Key Responsibilities:

• Lead an R&D organization developing 112G/224G Ethernet SerDes and Interface PHY IP for AI/HPC, networking, and data center markets
• Own execution planning, staffing, and delivery commitments across multiple concurrent programs and customer milestones
• Drive technical alignment across architecture, analog, digital, verification, firmware, and customer support teams
• Partner with product and program management to translate roadmap priorities into executable engineering plans
• Define processes for milestone reviews, risk management, and decision-making that keep programs moving
• Lead resolution of customer-critical issues from triage through root-cause analysis and corrective action
• Develop engineering talent through coaching, performance management, hiring, and succession planning

The Impact You Will Have:

• Deliver production-quality Ethernet SerDes IP that enables customers to meet performance and time-to-market goals
• Build execution discipline that consistently meets delivery commitments without burning out the team
• Establish quality practices that reduce post-release issues and customer escalations
• Develop future technical and managerial leaders through structured coaching
• Drive methodology improvements and automation that measurably improve productivity
• Shape the technical direction of next-generation SerDes platforms

Requirements:

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related discipline
• 15+ years of semiconductor development experience with progression into engineering leadership
• Proven experience leading engineering teams with significant schedule, quality, and customer impact
• Strong understanding of SerDes PHY digital development flows including architecture, RTL, verification, firmware, integration, and release
• Experience with Ethernet, PCIe/CXL, or other high-speed protocols; Ethernet SerDes experience strongly preferred
• Track record managing execution across distributed teams and multiple stakeholders

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support programs
• ESPP (Employee Stock Purchase Plan)
• Retirement plans
• Competitive salaries