Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent years turning RTL into silicon that actually works, not just passes checks, but works at speed, at power, under real-world conditions. You know that the difference between a design that tapes out clean and one that comes back with surprises is usually a floorplan decision made in week two or a timing constraint someone glossed over in the handoff. You catch those things before they become problems.
You are comfortable living in the space between synthesis and signoff, moving between Fusion Compiler, PrimeTime, and RedHawk without losing sight of what you are actually building. When a design does not close, you do not just run another iteration. You dig into the constraint, the cell placement, the IR drop map, and figure out what is actually wrong. You make calls without perfect information because waiting is not an option when tape-out is six weeks out.
You can talk to an IP architect about design intent and walk out with a floorplan that respects both performance and reality. You have been through enough tape-outs to know what good looks like, and you have strong opinions about methodology, constraints, and signoff quality. At Synopsys, you will work on interface IPs and subsystems that ship in products customers depend on, and the team will expect you to bring that judgment every day.
Own the complete physical implementation flow from RTL to GDSII for high-performance interface IPs, test chips, and subsystems at advanced nodes Drive synthesis, floorplanning, power planning, placement, clock tree synthesis, and routing using Synopsys tools including Design Compiler, ICC2, and Fusion Compiler Perform static timing analysis, EM/IR signoff, and physical verification to ensure designs meet all timing, power, and reliability targets Develop and refine implementation flows and CAD methodologies that improve turnaround time, PPA, and design predictability Interface directly with IP architects, verification teams, and product engineering to understand design constraints, deliverable formats, and customer requirements Debug complex timing, power, and physical issues across multi-million gate designs and make timely decisions under tape-out pressure Contribute to scripting and automation efforts using Perl, Tcl, and Python to streamline flows and improve design productivity