Chip Power Estimation Engineer

We are seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world's leading GPUs and SOCs. In this position, you will be responsible for developing advanced power models to estimate chip and board power under product-driven use cases. You will work with architecture, design, synthesis, timing, circuit, and post-silicon teams to accomplish your tasks.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

• Develop power estimation models and tools for NVIDIA's chips
• Help architect and develop power models for use-cases, idle power, and IO power
• Design tools based on these models and their testing methodology/infrastructures
• Correlate and calibrate the power models using measured silicon data
• Analyze and help decide the chip configuration and process technology options to optimize power/performance for NVIDIA's upcoming chips
• Help study and contribute to Performance/Watt improvement ideas for NVIDIA's GPUs and SOCs

Requirements:

• B.Tech./M.Tech and 2+ years of experience related to Power/Performance estimation and optimization techniques
• Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits
• Familiarity with low power design techniques such as multi-VT, clock gating, power gating, and dynamic voltage-frequency scaling (DVFS)
• Strong background in power estimation techniques, flows, and algorithms
• Good programming skills - Python preferred. Good skills with object-oriented programming and design.

Nice to Have:

• Exposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board-level power issues
• Exposure to power analysis EDA tools such as PTPX/EPS
• Good communication skills & desire to work as a great teammate